From f3f05a0ec584855c53f2d95024e23259f3ee101d Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Fri, 21 Mar 2025 20:47:23 +0800 Subject: [PATCH 2813/5403] drm/amdgpu: Use correct gfx deferred error count In the case of parsing GFX deferred error from SMU corrected error channel, the error count should be set to 1 instead of parsing from MISC0 register, which is 0. Signed-off-by: Xiang Liu Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 736398b0d16d..3caac4a1564a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -872,9 +872,10 @@ static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, break; case ACA_SMU_TYPE_CE: bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank); - ret = aca_error_cache_log_bank_error(handle, &info, - bank->aca_err_type, - ACA_REG__MISC0__ERRCNT(misc0)); + ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, + (bank->aca_err_type == ACA_ERROR_TYPE_CE) ? + ACA_REG__MISC0__ERRCNT(misc0) : + 1); break; default: return -EINVAL; -- 2.54.0